Silicon-on-insulator (SOI) semiconductor devices generally include a silicon island formed on the surface of an insulating material. Metal-oxide-semiconductor (MOS) transistors are formed in and on the silicon island. Additionally, it is known to form a complementary-metal-oxide-semiconductor (CMOS) device in an SOI structure. When the insulating material is a sapphire substrate, the structure is known as a silicon-on-sapphire (SOS) semiconductor device. However, the insulating material may also be a layer of silicon dioxide which is disposed on a semiconductor substrate. MOS/SOI transistors generally have higher speed and improved radiation hardness in comparison with MOS transistors formed in bulk silicon.
Referring now to FIG. 1, a conventional silicon-on-insulator semiconductor device is generally designated as 10. The device 10 is a silicon-on-sapphire semiconductor device because a silicon island 12 is formed on a sapphire substrate 14. The silicon island 12 is doped P-type; however, it also contains N-type source and drain regions 13 and 15, respectively. A gate oxide layer (not shown) is disposed on the surface of the silicon island 12 under at least the gate electrode 20. The device 10 actually consists of three transistors in parallel. The first transistor is formed on the top surface 16 of the silicon island 12. Two transistors are also formed along the opposed sidewalls 18 of the silicon island 12. The opposed sidewalls 18 lie under the gate electrode 20 and extend along the channel length of the SOS device. The transistors formed along the opposed sidewalls 18 are commonly referred to as parasitic edge transistors.
The parasitic edge transistors have a lower threshold voltage than the top transistor. When the parasitic edge transistors prematurely turn on, leakage currents are allowed to pass through the device. Additionally, when an N-channel SOI device is subjected to ionizing radiation, the edge transistor problem increases. Positive charges accumulate between the gate oxide and the silicon island. These positive charges shift the threshold voltage of the top and edge transistors. However, the threshold voltage shift is greater in the parasitic edge transistors. Thus, the edge transistors turn on well before the top transistor and this is a major cause of post-radiation leakage currents in SOI devices.
The dielectric strength of the gate oxide along the edge transistor is usually poor. This can be attributed to the non-uniform thickness of the gate oxide along the sidewall of the silicon island and the increased electrical fields around the silicon island edge. The poor dielectric strength of the gate oxide on the parasitic edge transistor and the increased electrical fields around the silicon island edge lead to premature gate breakdown. The premature gate breakdown is experienced in both N-channel and P-channel transistors.
In order to avoid the problem of the lower threshold voltage of the parasitic edge transistors, the sidewalls of the silicon island for an N-channel transistor are doped heavier than the channel region. This increases the threshold voltage of the edge transistor and thus reduces the post-radiation leakage currents. One such technique for doping the sidewalls of the silicon island is described in commonly assigned U.S. Pat. No. 3,890,632 entitled "Stabilized Semiconductor Devices And Method of Making The Same" which issued to W. E. Ham et al. on June 17, 1975. In an N-channel device, the sloped sidewalls of the silicon island are ion implanted with boron. However, the plasma etching techniques which are used today to define the silicon islands typically form vertical sidewalls. It is difficult to uniformly dope the vertical sidewalls of a silicon island using the ion implantation technique described by Ham et al.
Concentric edgeless semiconductor devices have also been developed to avoid the parasitic edge transistor problem. An example of such a device can be found in commonly assigned U.S. Pat. No. 4,185,319 entitled "Non-Volatile Memory Device" issued to R. G. Stewart on Jan. 22, 1980. The drain region of the transistor is enclosed by a frame-like gate electrode which is in turn surrounded by a frame-like source region. The frame-like gate is disposed totally on the top of the silicon island; therefore, the parasitic edge transistors are eliminated. Although the structure is indeed edgeless, it is quite large and can be used in integrated circuits or portions of integrated circuits where area considerations are unimportant.
There is a need in the art for small channel width and short channel length edgeless devices so that integrated circuits with high performance and high packing densities can be fabricated. Additionally, it would be desirable to form the short channel edgeless N-channel and P-channel transistors in a single semiconductor island so as to decrease the device area of CMOS integrated circuits.